The present invention relates to a semiconductor memory device, and particularly to an improvement of layout of sense amplifiers in a dynamic random access memory (DRAM) for higher integration.
Examples of DRAMs which are widely used are shown in FIG. 1 and FIG. 2, in which a pair of balanced halves of a bit line 4 are connected to a sense amplifier 1 formed of a flip-flop. Memory cells 15 are connected at the intersections formed by the bit lines 4 and word lines 14 orthogonal to the bit lines 4. FIG. 1 shows an open bit configuration in which halves of each bit line 4 extend toward opposite directions from the sense amplifier 1 and each word line 14 intersects only one half of each bit line 4. Input/output lines (data bus lines) 3 also intersect the bit line 4 and are connected to respective halves of each bit line 4 through a switch 2 controlled by a column decoder 5.
FIG. 2 shows a folded bit line configuration in which the halves of each bit line 4 extend in the same direction from the sense amplifier 1, and a word line 14 intersects both halves of the bit line 4. The folded bit line configuration is advantageous in that since the word lines 14 intersect both halves of the bit line 4, the effect of noise is minimized, so that the folded bit line configuration is used in DRAMs of 256 kbits or 1 Mbits. The open bit line configuration on the other hand is suitable for a higher integration because memory cells are connected at all the intersections between the bit lines 4 and word lines 14. With the advancement toward higher integration, the open bit line configuration is now drawing attention again and are considered as a good candidate for 16 Mbit memories, or 64 Mbit memories.
FIG. 3 shows another folded bit line configuration disclosed in Japanese Patent Application Laid-open No. 129460/1984 and Japanese Patent Application No. 208691/1982, in which sense amplifiers 1 are disposed on opposite ends of the bit lines 4 alternately, and one half of each bit line 4 connected to a sense amplifier 1 is disposed between two halves of another bit line 4. This configuration permits two sense amplifiers 1 to be disposed taking a space for four bit lines 4.
In summary, the folded bit line configuration has a limitation in that the memory cells 15 cannot be connected at all the intersections between the bit lines 4 and the word lines 14 and this imposes a limit to the increase in the degree of integration. In the open bit line configuration, each sense amplifier 1 must be disposed within the space, i.e., layout pitch, for one bit line 4, as shown in FIG. 4. This imposes a limit to the increase in the degree of integration.